Integrated circuitry, such as memory circuitry, often includes a series of closely spaced repeating conductive lines formed relative to a semiconductor substrate or underlying insulating layer. A never-ending goal in semiconductor processing is to provide smaller and denser circuits. Such results in conductive lines being placed closer and closer together. Electrical isolation therebetween becomes a greater and greater challenge. The lines are typically separated and electrically isolated by electrically insulating material. However, the adjacent conductive lines can effectively form capacitor plates, with the insulating material therebetween undesirably forming a capacitor dielectric layer. The parasitic or undesired capacitors which form can cause cross-talk between the lines, disrupting circuit operation.
One prior art technique of overcoming this problem is to use insulating materials having inherently low dielectric constants to avoid such capacitors from forming in the first place. However, deposition of such materials can be difficult to incorporate into conventional semiconductor fabrication processes. Regardless, the improvement in dielectric constant will typically still be insufficient to prevent considerable cross-talk between closely spaced lines.